1. Field of the Invention
The present invention relates to encoding and/or decoding information, for instance in optical recording systems. More particularly, the invention provides a method and system of coding information with improved information density, by imposing both modulation constraints and parity-check constraints in channel coded data sequences.
2. Description of the Related Art
Modulation codes, also known as constrained codes, are used in recording systems to translate an arbitrary sequence of user data into a sequence with special properties required by the relevant systems. Two major constraints for optical recording systems are run-length constraints, or (d, k) constraints, and the dc-free constraint. The run-length constraints bound the minimal and/or maximal lengths of runs of zeros in an encoded data stream, to mitigate the problems of intersymbol interference and inaccurate timing. The dc-free constraint avoids interference between data and servo signals, and also permits filtering of low-frequency disk noise, such as finger marks on the disk surface.
Coding and signal processing techniques play a key role in the development of high density and high speed optical recording systems. CD and DVD systems use modulation codes with the d=2 constraint and threshold-based receivers.
Reception techniques for the recently introduced third generation optical recording systems, i.e. blu-ray-disc (BD) or advanced optical disc (AOD), according to T. Narahara, S. Kobayashi, Y. Shimpuku, G. van den Enden, J. Kahlman, M. van Dijk, and R. van Woudenberg, “Optical disc system for digital video recording,” Jpn. J. Appl. Phys., pt. 1, vol. 39, no. 2B, pp. 912-919, 2000, and T. Iwanaga, S. Ogkubo, M. Nakano, M. Kubota, H. Honma, T. Ide and R. Katayama, “High-density recording systems using partial response maximum likelihood with blue laser diode,” Japan J. Applied Physics, vol. 42, no. 2B, part 1, pp. 1042-1043, February 2003, are significantly different from those used in CDs or DVDs. For example, the threshold detector is supplemented by more powerful Viterbi-like bit detection approaches, and the minimum run-length constraint is d=1 instead of d=2.
A new family of very efficient codes with the d=1 or d=2 constraints is proposed in U.S. Pat. No. 6,606,038, U.S. Pat. No. 6,639,524, and K. A. S. Immink, J. Y. Kim, and S. W. Suh, “Efficient Dc-free RLL codes for Optical Recording,” IEEE Trans. Commun, vol. 51, pp. 326-331, March 2003. The rates of the designed codes are greater than the rate 2/3 (1,7) codes used for BD and AOD, and the rate 8/15 (2,10) EFM-like code used for DVD. The capacity-approaching code rates are achieved by using specific efficient finite state machines (FSM) to reflect the d=1 and d=2 constraints. Furthermore, by combining the Guided Scrambling (GS) approach with the newly designed codes, satisfactory dc-free performance is achieved.
Higher recording capacity and data transfer rate systems need to utilise improved channel coding and detection schemes. In recent years, there has been much interest in constrained codes that have error correction properties. The reason is that, unlike the situation in conventional read channels, where the Reed-Solomon (RS) error correction code (ECC) is expected to correct all the errors that occur at the output of the constrained decoder, the most probable (also called dominant) error events can be corrected by the application of a distance enhancing parity-check code. This parity-check code is an inner block-ECC, which is used separately from the outer RS-ECC. It may correct dominant short error events that occur at the output of the channel detector, using only a few redundant parity-check bits. In this way, the correction capacity loss of the outer ECC is significantly reduced and the error propagation of the modulation decoder is also minimised, thus resulting in a simple and efficient solution to improve the overall performance. Compared with iteratively decodable codes, such as turbo codes or low density parity-check codes, the parity-check codes based approach has found wide acceptance in data storage systems, since the performance-complexity trade-off offered by these codes is very attractive and affordable. Therefore, it is one of the most promising reception techniques for so-called ‘fourth generation’ optical storage systems.
Parity-check codes may be classified into single-bit parity-check codes and multiple-bit parity-check codes. A single-bit parity-check code with even (or odd) parity-check is a simple and basic code, which can detect only a few types of error events. For improved performance, multiple-bit parity-check codes are preferred, according to K. Cai, V. Y. Krachkovsky, and J. W. M. Bergmans, “Performance bounds for parity coded optical recording channels with d=1 constraint”, Proc. of IEEE International Conference on Communications (ICC), Alaska, USA, May 2003, and H. Sawaguchi, S. Mita, and J. K. Wolf, “A concatenated coding technique for partial response channels,” IEEE Trans. Magnetics, vol. 37, No. 2, pp. 695-703, March 2001, since such codes can detect many more types of error events in one data block, and provide more side information for error correction.
When a parity-check constraint is imposed on a channel bit stream, the modulation constraints should be simultaneously satisfied. As a result, a certain code rate loss will be incurred. Therefore, the design of efficient constrained parity-check codes is key to the development of parity-check code based receivers. Although many attempts have been made by researchers in recent years to combine a constrained code with a parity-check code efficiently, the systematic design of constrained parity-check codes with minimum code-rate loss remains an open problem. It is especially difficult to design constrained parity-check codes that satisfy multiple-bit parity-check constraints for optical recording systems.
In one scheme described by P. Perry, M. C. Lin, and Z. Zhang, “Runlength-Limited Codes for Single Error-Detection and Single Error-Correction with Mixed Type Errors,” IEEE Trans. Inform. Theory, vol. 44, no. 4, pp. 1588-1592, July 1998, a constrained data sequence is parsed into shorter pieces of equal length. Between each pair of the constrained data block, a parity data block is inserted for error control. The constrained data blocks and parity data blocks are connected such that no violation of the modulation constraints occurs. The advantage of this scheme is the lack of error propagation. However, it still has general losses, since only specific mixed-type errors for the magnetic recording system can be corrected. Furthermore, its coding efficiency is low. For detection of a single mixed-type error, parity blocks of length 2d+3 are required.
Concatenated coding is further proposed to construct modulation codes with error detection and correction capabilities, as discussed in S. Gopalaswamy and J. W. M. Bergmans, “Modified target and concatenated Coding for constrained magnetic recording channels,” in Proc. IEEE Intl. Conf. Commun. (ICC), New Orleans, USA, June 2000, pp. 89-93 and H. Sawaguchi, S. Mita, and J. K. Wolf, “A concatenated coding technique for partial response channels,” IEEE Trans. Magnetics, vol. 37, No. 2, pp. 695-703, March 2001. In the concatenated coding scheme, parity-check information is first calculated for each modulation coded data block. This information is then separately encoded by a standard constrained encoder and appended to the end of the corresponding modulation data block. In this way, the concatenated coding scheme achieves high coding efficiency. For a d=2 code with rate around 0.5, a parity-check bit requires 2 channel bits. For a rate 2/3 (1,7) code, a parity-check bit requires 1.5 channel bits. However, the concatenated coding scheme has two drawbacks: (i) during decoding, local demodulation is needed to derive the parity-checks. Thus, part of the channel bit-stream corresponding to the parity-check bits needs to be modulation decoded first, before the parity-check information for the combined data block can be obtained. Obviously, this will increase the decoding complexity. (ii) the channel bit-stream corresponding to the parity-check bits is not protected by parity-checks. Therefore, errors occurring in the parity-related data block may lead to further errors during the decoding of the whole data block. Thus results in error propagation.
A combi-code scheme (proposed in US patent publication US A1 2003/0028839 and by W. Coene, H. Pozidis, J. Bergmans in “Run-length limited parity-check coding for transition-shift errors in optical recording”, in Proc. IEEE Intl. Conf. Global Telecommun. [GLOBECOM], San Antonio, November 2001, pp. 2982-2986) also achieves high efficiency similar to the concatenated scheme, without introducing error propagation. According to this scheme, the constrained parity-check code consists of a set of two sliding block codes: a standard code and a parity-check enabling code. The leading part of the constrained parity-check code includes several standard codes, which are chosen to be conventional constrained codes. At the end of the constrained parity-check code, a parity-check enabling code is used to realise a certain parity-check on the whole code word. Because the two constituent codes are based on the same FSM, no additional channel bits are needed for stitching the two codes together. In this way, high efficiency d=2 constrained parity-check codes, which achieve 2 channel bits per parity-check bit, have been designed. However, the combi-code scheme has several drawbacks.
First, the combi-code scheme is designed to correct a specific type of error event (i.e. single-bit transition shift error, or n-bit transition shift errors in the same direction). It is difficult to generalise the scheme to detect an arbitrary type of error event as well as error event combinations.
Second, the combi-code scheme achieves high efficiency only for d=2 codes. For d=1 codes that are used in third generation optical recording systems, highly efficient combi-codes are not available. Coene et al. (cf. above) proposed that high efficiency d=1 codes can be obtained by either (i) using a sophisticated time-varying encoder, or (ii) combining parity-check enabling codes with dc-free enabling codes. The disadvantage of a time-varying encoder is that, for each phase of the encoder, a separate code is required. This will cause significant increases in the implementation complexity. On the other hand, the combination of parity-check enabling codes with dc-free enabling codes will weaken the dc-suppression. This is because, to get a satisfactory dc-suppression, dc-free enabling codes need to be inserted more frequently than the parity-check enabling codes.
Third, the main component code (i.e. the standard code) used by the combi-code scheme is still a rate 2/3 (1,7) code for d=1 constraint, and a rate 8/15 (2,10) code for d=2 constraint. The efficiency of both the standard codes and the parity-check enabling codes could be further improved by using the state splitting method proposed by Immink et al. (cf. above).
The present invention overcomes the above-mentioned drawbacks of the prior art schemes. More particularly, the present invention provides a general and systematic way for constructing capacity-approaching constrained codes with any given parity-check constraint, which can detect and correct any type of dominant error event as well as error event combinations, for instance in optical recording systems.